Layout-aware Analog Synthesis Based on Multi-level Optimization, Performance Model Approximation and Solution Space Pruning

This paper presents a new multilevel optimization algorithm for layout-aware synthesis of analog systems. The synthesis methodology integrates (1) block parameter search, (2) block placement, and (3) global interconnect routing while maintaining an accurate perspective about layout parasitic. Multilevel optimization conducts a sequence of exploration steps, in which each step uses performance models of superior accuracy (with respect to the previous steps), while searching reduced parameter domains. The paper defines original algorithms for design parameter abstraction, abstraction error evaluation, and design space pruning. Theoretical and experimental results show a superior convergence of the multilevel algorithm ascompared to flat exploration. Execution time is also much improved without trading-off quality.